As the level of integration continues to advance, many complex electronic logic systems can now be implemented on a single integrated circuit (IC). Such an IC, often known as “system on a chip (SoC)” or “ultra large scale integrated circuit (ULSI)” in the art, includes multiple complex components (e.g., micro-processor, digital signal processor, peripheral and memory controllers), many of which may be individually obtained as “off-the-shelf” electronic circuit designs from numerous vendors in the market. These electronic circuit designs are known as “IPs1” to those skilled in the art. 1 The term “IP” stands for “intellectual property.” Designers of these electronic circuits provide the designs to their customers in the form of data files which are readable by popular electronic design automation (EDA) tools. The customers of these designers then integrate these “IPs” into their own circuit designs. As an IP vendor does not provide a manufactured article here—the electronic deign is typically provided as design data represented in electronic form (e.g., stored in a storage medium, such as a compact disk, or as a stream of bits downloaded from a server via the Internet)—it has become customary in the art to refer to such electronic circuit design products as “IPs”.
In U.S. Pat. No. 6,701,491, entitled “Input/output probing apparatus and input/output probing method using the same, and mixed emulation/simulation method based on it” by Yang, an interactive environment is disclosed for IC designers to conduct emulation sessions back and forth between a hardware accelerator and a software simulator. Correspondingly, memory states and logic storage node states are swapped between the accelerator and the simulator. A complete context switch is performed to create a time-shared environment on the hardware accelerator, so that the hardware accelerator can be shared among multiple IC designers. In general, in a similar manner, multiple accelerators can be interconnected with multiple simulators and multiple workstations to allow multiple designers to do interactive operations and to shift back and forth between hardware emulation and software simulation.
A mixed emulation and simulation method is also disclosed by Yang. Here, input/output hardware probing is performed by emulation for verification. At least one semiconductor chip is used which implements an extended design verification target circuit by adding an IOP-probing supplementary circuit to the design verification target circuit. The IOP-probing supplementary circuit includes an input/output probing interface module. In this system, an input/output probing system controller generates the IOP-probing supplementary circuit for the design verification target circuit. The design verification target circuit is implemented in one or more semiconductor chips mounted on a prototyping board or specified by a hardware description language (HDL) code—which indicates the behavior of the IOP-probing supplementary circuit—for simulation on a simulator. Emulation and simulation are then performed in turn for one or more times, as necessary, by exchanging state information in an automated manner between a suitable prototyping board and a suitable simulator. Furthermore, the state information is completely exchanged in an automated manner between the prototyping board and the simulator by the IOP-probing supplementary circuit-based input/output probing. With the IOP-probing supplementary circuit, another mixed emulation/simulation process is also disclosed whose operating mode is conditionally based upon a pre-determined switching condition queue on a time order, switched between simulation and emulation during the process until the operating mode switching queue becomes empty.
In U.S. Pat. No. 6,389,379 entitled “Converification system and method” by Lin, et al, a coverification system and an associated method are disclosed. The coverification system includes a reconfigurable computing system and a reconfigurable computing hardware array. The reconfigurable computing system contains a CPU and memory for processing data for modeling the entire user design in software. In some instances, a target system and external I/O devices are not necessary, as they can be modeled in software. In other instances, the target system and external I/O devices are coupled to the coverification system to achieve speed and to allow use of actual data, rather than simulated test bench data.
The disclosed coverification method by Lin, et al was directing at verifying the proper operation of a user design, while the user design connected to an external I/O device. The method generates a first model of the user design in software for use in simulation, generates a second model of a portion of the user design in hardware, which is controlled by the first model in the software. More specifically, in this system, the data evaluations in the first model in software and the second model in hardware are synchronized using a software-generated clock. For debugging, the method simulates selected debug test points in software, accelerates selected debug test points in hardware and controls the delivery of data among the first model in software, the second model in hardware, and the external I/O device so that the first model in software has access to all delivered data.
In the prior art, designing, debugging, verifying and validating a system that includes a user design integrated with one or more third party IPs is generally difficult, as the user often starts with designing a behavior description or a simulation model of the IP with incomplete control over the IPs logical behavior at the interfaces between the user design and the IPs. In addition, user designs that are specified by behavior simulation models, logic gates and embedded software are extremely difficult to create. In such a system, it is also difficult to isolate system faults. For example, it is difficult to discover errors within an audio or video output data stream, unless the user can “hear” or “see” the rendered audible or visual results. A conventional design verification and validation method therefore prototypes (architects) the system behavior in an EDA (EDA) simulation environment to verify the numerous interface functions. Afterwards, the system separately embodies the EDA-simulated logic into custom application reference board-based validation environments to “hear” or “see” the audible or visual results. The final step in the prototyping involves incorporating the logic into packaged electronic devices according to product-level electrical specification. During this conventional process of design verification and validation, for example, incorrectly behaving output signals of an audio or video decoder due to logic, algorithmic or software programming errors in the user design may manifest themselves in unpredictable audio or display behavior. For a complicated system, unpredictable behavior potentially caused by a logic, algorithmic or software programming error is extremely difficult to diagnose and isolate, whether in the EDA simulation or the application reference board environment. Therefore, a design verification and validation method with associated tools that allows the user (1) to integrate his EDA prototyping simulation process directly with his printed circuit board (PCB) prototype, (2) to quickly isolate or fix design faults, and (3) to quickly verify and validates his PCB prototype in an integrated environment is highly desirable. In essence, such a design verification and validation method would provide the user with a high throughput, end-to-end solution from design verification to system validation.